Alif Semiconductor /AE722F80F55D5LS_CM55_HE_View /USB /GSBUSCFG0

Undefined length INCR burst type enable. This bit determines the set of burst lengths the master interface uses. It works in conjunction with the GSBUSCFG0[7-1] bits enables (INCR256/128/64/32/16/8/4). ARLEN/AWLEN do not use INCR except in case of non-aligned burst transfers. In the case of address-aligned transfers, they use only the following burst lengths:

• 1
• 2, 4 (if GSBUSCFG0[INCR4BRSTENA] = 0x1)
• 8 (if GSBUSCFG0[INCR8BRSTENA] = 0x1)
• 16 (if GSBUSCFG0[INCR16BRSTENA] = 0x1)
• 32 (if GSBUSCFG0[INCR32BRSTENA] = 0x1)
• 64 (if GSBUSCFG0[INCR64BRSTENA] = 0x1)
• 128 (if GSBUSCFG0[INCR128BRSTENA] = 0x1)
• 256 (if GSBUSCFG0[INCR256BRSTENA] = 0x1) Note: In case of non-address-aligned transfers, INCR may get generated at the beginning and end of the transfers to align the address boundaries, even though INCR is disabled. AXI: ARLEN/AWLEN uses any length less than or equal to the largest-enabled burst length of INCR32/64/128/256.

0 (Val_0x0): INCRX burst mode.

1 (Val_0x1): INCR (undefined length) burst mode.

INCR4 burst type enable. When this bit is enabled (set to 0x1), the controller is allowed to do bursts of beat length 1, 2, and 4. It is highly recommended that this bit is enabled to prevent descriptor reads and writes from being broken up into separate transfers.

INCR8 burst type enable. If software set this bit to 0x0, the AXI master uses INCR to do the 8-beat burst.

INCR16 burst type enable. If software set this bit to 0x1, the AXI master uses INCR to do the 16-beat burst.

INCR32 burst type enable. If software set this bit to 0x1, the AXI master uses INCR to do the 32-beat burst.

INCR64 burst type enable. If software set this bit to 0x1, the AXI master uses INCR to do the 64-beat burst.

INCR128 burst type enable. If software set this bit to 0x1, the AXI master uses INCR to do the 128-beat burst.

INCR256 burst type enable. If software set this bit to 0x1, the AXI master uses INCR to do the 256-beat burst.

Descriptor access is big endian. This bit controls the endian mode for descriptor accesses. Data is considered as embedded data in the descriptors in the following cases:

• Device mode: The buffer pointer of a Setup TRB points to the Setup TRB itself. In device mode, if the system uses different endian modes for descriptor and data, software must not use embedded data.
• Host mode: The Immediate Data (IDT) bit in a Transfer TRB is set to 0x1. In host mode, if the system uses different endian modes for data and descriptors, the controller treats embedded data as descriptor (not as data) in terms of endian mode handling. If this is not the expectation of the system, the software must manipulate the embedded data accordingly. Note: For an AXI master, this bit must be set to 0x0.

0 (Val_0x0): Little-endian (default)

1 (Val_0x1): Big-endian

Data access is big endian. This bit controls the endian mode for data accesses. Note: For an AXI master, this bit must be set to 0x0.

0 (Val_0x0): Little-endian (default)

1 (Val_0x1): Big-endian

Descriptor write request info. AHB-prot/AXI-cache/OCP-ReqInfo for descriptor write.

Data write request info. AHB-prot/AXI-cache/OCP-ReqInfo for data write.

Descriptor read request info. AHB-prot/AXI-cache/OCP-ReqInfo for descriptor read.

Data read request info. AHB-prot/AXI-cache/OCP-ReqInfo for data read.